Verification of Initialization Sequences for Sequential Circuits
نویسندگان
چکیده
منابع مشابه
Timing verification of sequential dynamic circuits
This paper addresses static timing verification for sequential circuits implemented in a mix of static and dynamic logic. We restrict our focus to regular domino logic and footless domino logic, a variant of domino logic. First we derive constraints for proper operation of dynamic gates. An important observation is that for dynamic gates, input signals may start changing near the end of the eva...
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ژورنال
عنوان ژورنال: Electronics And Electrical Engineering
سال: 2011
ISSN: 2029-5731,1392-1215
DOI: 10.5755/j01.eee.112.6.446